This area of 'interest' is for the hardware design ecosystem for Arm based System on Chip developments. This area is for discussion of design techniques. Specific design flow actions should be discussed in the design flow section.

Designing components and systems with an emphasis on minimizing active (dynamic) and standby (static) power consumption. Increasingly this is addressed by careful logical design of the design in RTL together with companion "power intent", provided as Unified Power Format (UPF) annotation, standardized in IEEE 1801 specification.

When designing a high-speed chip, whether that is for high-speed digital applications or analog wireless applications, radio frequency (RF) design is involved.  RF design is also a component of chip packaging and off-chip interfaces, where high-speed digital buses, transmission lines, and other RF components need to be "impedance-controlled". Emerging applications of RF design involve on-chip communication using wireless links and networks-on-chip.

Once a System on Chip (SoC) design has fabricated in a foundry the individual items need to be put into an  electronic package that protects it from the external environment and also interconnects it to other parts of a larger system, often a Printed Circuit Board. The package may also need to perform other functions such as transfer of heat or protection from emissions that could affect device performance.

The Machine Learning 'interest' area covers topics at the intersection of Machine Learning and SoCs from both the hardware and software perspective.

Welcome to the Student Area! No matter if you are SoC design noob making your first steps into the world of SoCs  or an experienced postgraduate student planning to make a tape-out, this is the place to find guidance for your first designs, ask questions and exchange information with other students working in the same field. The Student Area is organised as follows: SoC Noobs - A guide for your first steps in SoC design Student Journeys - What I wish new when I started Discussion board - Ask questions and express ideas One of the key aims for SoC Labs is to create

SoC Labs is in one view a shared repository of resources, tools and other materials to help you in your System on Chip development activity. More importantly in our view, it is a collection of experience and a way to have many potentially beneficial collaborations. The community of people engaged with SoC Labs are working on some of the most interesting work in System on Chip development.

This area of 'interest' is for the software ecosystem for Arm based System on Chip developments. Software covers a large field of activity from basic boot sequence, firmware, operating system kernel, device drivers, middleware and application level.   

In computer programming and software development, debugging is the process of finding and resolving bugs (defects or problems that prevent correct operation) within computer programs, software, or systems. Debugging tactics can involve interactive debugging, control flow analysis, unit testing, integration testing, log file analysis, monitoring at the application or system level, memory dumps, and profiling. Many programming languages and software development tools also offer programs to aid in debugging, known as debuggers.

The definition of firmware varies but most describe a specialist form of software that is by design tightly coupled to hardware behaviour and intrinsically linked to the operation of the hardware. In some systems the definition can be simplified by where it is physically stored or how it is executed by a processor. Development of firmware may require assembly programming (an understanding of the Arm instruction set).

Is not a programming language, it is an IEEE Standard C++ class library for system and hardware design. Knowledge of the SystemC library allows it to be extended using the C++ language to enable SoC design and verification activities. A SystemC application usually has an elaboration phase during which a module hierarchy is instantiated that represents the hardware design for the system, followed by a simulation phase using a simulation engine which is formed as part of the core of the SystemC library which schedules the user defined processes that simulate the design. Arm provides a num

This area of interest is for this web site, the SoC Labs community portal. Here we discuss the site's structure, operations and any issues the community feel need improvement.  If you are new to SoC Labs, then knowing how we structure information on the site will help. Projects: As a community activity we form our collaborations around shared Projects.

All content on the SoC Labs portal is moderated. This is to ensure the content is useful to the community. Once signed up, you can make suggested changed to material on the portal, create new material, etc.

Projects Community centric hardware design projects are the core activity of the SoC Labs. We are keen to share information on projects much earlier than traditional academic sharing. Historically knowledge sharing has been at the end of the research activity, with published papers and results. We are keen to get collaborations started much earlier. So as well as write up of finished projects ("case studies"), ongoing projects under development ("projects") and even projects that are still being formulated ("request for collaboration") are listed.