Hardware Design Learning Hub

A comprehensive guide through every phase of digital hardware design — from architecture to silicon validation.

Phase 2 · 4 topics

RTL Design

Write the Register Transfer Level code that describes your hardware in synthesisable Verilog or SystemVerilog.

Overview

An introduction to the RTL Design phase and what you'll learn.
Behavioural Modelling
Simulation
Generate RTL
RTL Verification
Phase 3 · 3 topics

Verification

Rigorously test your design to ensure it meets the specification before committing to silicon.

Effort
Uncertainty
Overview

An introduction to the Verification phase and what you'll learn.
Technology Selection
Effort
Uncertainty
Design for Test
Logical verification

Logical verification is...
Phase 4 · 0 topics

Synthesis

Transform your RTL into optimised gate-level netlists targeting your chosen technology — FPGA or ASIC standard cells.

 


 

Effort
Uncertainty
Overview

An introduction to the Synthesis phase and what you'll learn.
Phase 5 · 3 topics

Physical Design

Transform your gate-level netlist into a physical layout ready for fabrication — floorplanning, placement, routing, and sign-off.

Overview

An introduction to the Physical Design phase and what you'll learn.
Floor Planning
Routing
Timing closure
Phase 6 · 0 topics

Tapeout

Prepare and submit your final design database (GDSII) for fabrication through a shuttle service.

Overview

An introduction to the Synthesis phase and what you'll learn.
Phase 7 · 0 topics

Silicon Validation

Validate your fabricated chips — bring-up, characterisation, and debugging on real silicon.

Overview

An introduction to the Synthesis phase and what you'll learn.