Technology | SoC Labs

Any System On Chip usually involves the use of pre-existing IP blocks and some novel parts specific to the SoC. Here you will find summaries of the technologies associated with SoC Labs either from the core Arm Academic Programme (link) or provided by the community. You can use the navigation scheme above for a tree view to get more details for each technology.

We are always looking to add additional IP blocks, resources and references to community work. For example in the section 'Security' link (https://soclabs.org/technology/security) you will find both the Arm IP (True Random Number Generator) and a PUF implementation from Basel Halak at Southampton. We hope members will add information and items that the community can share and benefit from in developing their SoC implementations as well as their own expertise or interest. If there is anything you feel might be helpful do let us know.

Communication

A System on Chip (SoC) usually has many functional blocks to deal with communication either on chip or the the external environment. For on chip communication the Advanced Microcontroller Bus Architecture is a common bus architecture. For more complex many core devices Network On Chip (NoC) protocols are adopted for communication between various components.

Advanced Microcontroller Bus Architecture

Any System On Chip requires a bus mechanism to allow functional parts to exchange data. The ARM Advanced Microcontroller Bus Architecture is an open-standard, royalty-free, platform-independent, architecture for the connection and management of functional blocks in System On Chip design.

CoreLink NIC-400

CoreLink NIC-400 can be used to create the Advanced Microcontroller Bus Architecture compliant Interconnect communication path between the functional blocks of the System on Chip.

CoreLink NIC-450

The CoreLink NIC-450 provides additional Arm blocks to extend the NIC-400 capabilities: QoS-400 Network Interconnect Advanced Quality of Service provides regulation of read and write request to manage traffic for specific latency applications. QVN-400 Network Interconnect Advanced QoS for Virtual Networks provides buffer space for virtual channels in the interconnect and the Dynamic Memory Controller (DMC) in the SoC to avoid blocking between different data flows. TLX-400 Network Interconnect Thin Links reduces the number of signals in an AXI point-to-point connection allowi

CoreLink CCI-400

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.

CoreLink CCI-500

CCI-500 Cache Coherent Interconnect provides high bandwidth access between CPUs and other SoC blocks including shared main memory and enables use of Arm big.LITTLE processing techniques between multiple cores. It supports up to four ACE masters, Arm processors, six ACE-Lite masters, eg. Mali GPU and six AXI4 slaves for memory, system peripherals, etc. It implements a snoop filter within the interconnect that maintains a directory of all cache contents which avoids broadcasting coherency messaging to all agents improving latency and power consumption over the CCI-400.

CoreLink CCI-550

CCI-550 provides high bandwidth access between CPUs and other SoC blocks including shared main memory supporting Arm big.LITTLE processing techniques with up to seven ACE/ACE-Lite masters ACE (max 6) for Arm processors, ACE-Lite (max 6) Mali GPU, etc. and seven AXI4 slaves for memory (max 6), system peripherals, etc. It implements a snoop filter within the interconnect that maintains a directory of all cache contents which avoids broadcasting coherency messaging to all agents improving latency and power consumption over the CCI-400.

CoreLink ADB-400

ADB-400 AMBA Domain Bridge can form an asynchronous bridge between two components either as a Dynamic Voltage Frequency Scaling (DVFS) bridge with slave and master domains in different voltage domains or a clock bridge in the same voltage domain.

XHB-400: AXI4 to AHB-Lite Bridge

The XHB-400 has an AXI4 slave and AHB-Lite master interfaces and converts AXI4 to the AHB-Lite protocol with configurable data widths and zero latency conversion.

Bluetooth LE

Offering a direct interface to the user through smartphones, Bluetooth and Bluetooth Low Energy (BLE) operate at 2.4 GHz and support a variety of network architectures including mesh networks, beacons, as well as point-to-point links. BLE transceivers are becoming increasingly low in power consumption and are widely integrated in digital chips with low operation voltage and very small sleep current draw. Realizing a BLE-connected SoC involves on- and off-chip RF design elements such as power amplifiers (on-chip) and antennas (off-chip).

Near Field Communication (NFC)

Near Field Communication (NFC) relies on near-field electromagnetic coupling to securely transmit information wirelessly between compatible devices. NFC is widely used in authentication with NFC hardware becoming part of most smartphones. NFC emerged as a sub-class of RFID, now operating at 13.56 MHz, with additional security features. Owing to its non-radiative nature, NFC can be used safely in body-centric applications, at higher power levels and with lower losses than higher frequency RF data transmission approaches.

High-Frequency (HF) and Ultra High-Frequency (UHF) radio frequency identification (RFID) are becoming pervasive technologies in retail and industrial applications. RFID chips are passive and rely on the reader to provide power and information wirelessly before relaying the tag's ID back using the same wave. RFID tags have applications in sensing and show the potential for enabling battery-free SoCs with computational capabilities to be powered in the same way.

Widely used in enabling wireless internet connectivity at high data rates, Wi-Fi mostly operates in the 2.4 GHz band alongside Bluetooth and other IEEE 802.15 standards and is based on the IEEE 802.11 standard. Wi-Fi offers high power efficiency relative to its data rate and can operate at 5 GHz (WiMax) and around 60 GHz for short-range high-capacity links, where Gbit/s data rates with very low latencies can be achieved.

Cortex-A Series

The Arm Cortex-A series is a class of application processors that implement a Virtual Memory System Architecture (VMSA) that enable Operating Systems such as Linux to support the operation of multiple software applications. The specific processor may support multiple levels of execution, separating applications usually running unprivileged and operating system functions running in privileged modes allowing the protection of the system from malfunctioning applications.

The Cortex-A53 processor has an 8-stage, symmetric dual-issue in-order pipeline implementing the 64-bit Armv8-A architecture with one to four cores with automatic data cache coherency, the shared Level 2 cache can be up to 2MB, 128 bit ACE or CHI coherent system bus interface. The A53 pipeline supports symmetric dual-issue of most instructions, compared to the A7 which can only handle integer instructions in the second slot.

The Cortex-A35 processor is Arm’s most power-efficient application processor capable of seamlessly supporting 32-bit and 64-bit code. Supports one to four cores with automatic data cache coherency, a shared Level 2 cache, 128 bit ACE, CHI or AXI system bus interface. The A35 has thirty-one 64-bit general-purpose registers instead of fifteen 32-bit registers in the A7.

The Cortex-A34 processor has an 8-stage, in-order pipeline implementing the 64-bit Armv8-A architecture with one to four cores with automatic data cache coherency, a shared Level 2 cache, 128 bit ACE, CHI or AXI system bus interface. It has hardware virtualization support.

The Cortex-A32 processor has an 8-stage, in-order pipeline implementing the 32-bit Armv8-A architecture with one to four cores with automatic data cache coherency, a shared Level 2 cache, 128 bit ACE, CHI or AXI system bus interface improving efficiency over Cortex A7 and A5. Cortex-A32 can be configured as a uniprocessor without coherency logic or with Advanced Coherency Extensions (ACE) bus for fully coherent multiprocessing systems. The A32 Armv8-A has hardware virtualization support.

The Cortex-A7 processor builds on the energy-efficient 8-stage in-order pipeline of the Cortex-A5 processor, adding up to 1 MB Level 2 cache, 40 bit physical addressing to support Large Physical Address Extensions (LPAE), 64-bit load-store and 128-bit AMBA ACE bus. The Cortex-A7 processor provides up to 20% more single thread performance than the Cortex-A5. The Cortex-A7 implements the ARMv7-A architecture with one to four processors in a multiprocessor configuration with an optional integrated Generic Interrupt Controller (GIC) that is compliant with the version 2.0 of the ARM Generic I

Cortex-A5 (UP and MP)

The Cortex-A5 processor (UP uniprocessor or MP multiprocessor) has an 8-stage in-order pipeline with dynamic branch prediction, 32 bit physical addressing, Level 1 cache, 64-bit AXI master interface and optionally either a Floating-Point Unit or a NEON Media Processing Engine.

Cortex-M Series

The Cortex-M processors are aimed at microcontroller and embedded applications with a 32-bit architecture (Armv7-M supports the Thumb and Armv8-M a variant of the Thumb 32 instruction set), a Protected Memory System Architecture (PMSA) and run dedicated operating systems. The year of introductions are, M3 (2004), M0 (2009), M4 (2010), M0+ (2012), M7 (2014), M23/M33 (2016)

The Cortex-M55 implements the Arm v8.1-M Mainline architecture with a four stage in-order integer pipeline and M-profile Vector Extension (MVE) benefitting machine learning and signal processing applications. MVE has 8 vector registers of 128-bit width for Helium instructions and Custom Instructions for external co-processor accelerators.

The Cortex-M33 implements the ARMv8-M architecture with a three stage in-order pipeline supporting Thumb-1 and Thumb-2, single precision Floating Point Unit, Digital Signal Processing (DSP), saturated and Custom Instructions for external co-processor accelerators. The Nested Vector Interrupt Controller (NVIC) supports up to 480 interrupt inputs from peripherals with between 8 and 256 levels of priority. TrustZone support for a Secure and a Non-secure state The Memory Protection Unit supports the PMSAv8 Protected Memory System Architecture model with up to 16 regions. The bus mechanis

The Cortex-M23 implements the ARMv8-M architecture with a two-stage in-order pipeline supporting Thumb-1 and subset of Thumb-2 instructions with hardware multiply and divide in a low gate count similar to M0 and aimed at energy efficient embedded applications. The Nested Vector Interrupt Controller (NVIC) supports up to 240 interrupt inputs from peripherals with 4 priority levels supporting deterministic and fixed-latency interrupt handling. TrustZone support for a Secure and a Non-secure state The Memory Protection Unit supports the PMSAv8 Protected Memory System Architecture model with up

The Cortex-M7 implements the ARMv7E-M architecture using a 6 stage superscalar pipeline with branch prediction, instruction and data caches (64 bit buses) and tightly coupled memories (TCMs) to give nearly double the performance of M4 processor. Double precision instructions are added to the IEEE 754 compliant Floating Point Unit, Digital Signal Processing (DSP) and Thumb-1 and Thumb-2 instructions. A Memory Protection Unit supporting 8 or 16 protection regions to separate processes and privileges. The bus mechanism implements a 64-bit AMBA4 AXI, 32-bit AHB peripheral (AHBP) port, 32-bit AH

The Cortex-M4 implements the ARMv7-M architecture adding IEEE 754 compliant single precision Floating Point Unit and a range of saturating and SIMD instructions for Digital Signal Processing (DSP). Supports Thumb-1 and Thumb-2 instructions with a 3-stage in-order pipeline, with hardware Divide and Multiply, privileged and nonprivileged mode (User Thread). It supports Bit-banding regions in the lowest 1MB of the SRAM and Peripheral memory allowing individual bits to be toggled without performing a read-modify-write. The Nested Vector Interrupt Controller (NVIC) supports up to 240 interrupt i

The Cortex-M3 implements the ARMv7-M architecture supporting Thumb-1 and Thumb-2 instructions with a 3-stage in-order pipeline, with hardware Divide and Multiply, and an additional nonprivileged mode (User Thread). It supports Bit-banding in the lowest 1MB of the SRAM and Peripheral memory allowing individual bits to be toggled without performing a read-modify-write. The Nested Vector Interrupt Controller (NVIC) supports up to 240 interrupt inputs from peripherals with programmable priority levels from 8 to 256 levels. The bus mechanism implements the 3x AHB-lite protocol interfac

The Cortex-M0+ implements the ARMv6-M architecture with a two-stage in-order pipeline and additonal clock gating to improve efficiency and a Memory Protection Unit supporting 8 protection regions to separate processes and privileges in the same gate count as MO. Supports Thumb (16 bit) and subset of Thumb-2 (32/16 bit) instructions.

The Cortex-M0 is a 32 bit processor is targeted at SoCs that require a low gate count (12-25k gates), small die area, high energy efficiency (0.012 mW/MHz Min Power with 50 MHz Max Freq) and is intended for microcontroller and embedded applications. The processor core implements the ARMv6-M architecture and supports In-order execution.

Cortex-R Series

The Cortex-R Series is aimed at embedded Systems for precisely defined applications with either deterministic real time performance or safety critical demands.

The Cortex-R52 processor implements the ARMv8-R architecture allowing support for a hypervisor and hosting multiple operating systems. Allows up to four processing units (quad-core) / 8 logical cores in Dual Core Lock Step (DCLS) using redundant cores in lockstep for fault detection.

The Cortex-R8 processor implements the ARMv7-R architecture. Allows up to four processing units (quad-core) running independently, each executing its own program with its own bus interfaces (Asymetric) or with a single operating system managing all cores (Symertric).

The Cortex-R5 processor implements the ARMv7-R architecture. Allows up to two processing units (dual-core) with either Dual Core Lock Step (DCLS) using one core redundantly in lockstep for fault detection or the cores each executing their own program with independent bus interfaces (Asymetric).

Accelerators

Mali Graphics Processor Unit (GPU) use 16x16 pixel tile-based rendering to minimize external memory accesses keeping the entire working set for a tile in fast on-chip memory tightly coupled to the shader core. Processing takes two passes, the first executes all the geometry processing and generates a tile list data structure of primitives that contribute to each tile, the second executes all the fragment processing, tile by tile, each write to memory is a final state tile. The Mali architecture has benefits for some operations such as anti-aliasing while other operations such as tess

Ethos-U55 is a micro Neural Processing Unit coprocessor to accelerate machine learning inference with a configurable 32 to 256 multiply-accumulate (MAC) engine. One of the features to minimise memory use is that weights are losslessly compressed as part of a compiled command stream with the unit undertaking weight decompression. The unit executes the command stream with local DMA access to system memory.

The G52 implements the Bifrost architecture supporting OpenGL 2.0 and Vulkan and Machine Learning (ML) and Augmented Reality (AR) with support for 8 bit dot product operations.

SoC Labs Accelerator Wrapper

In order for an accelerator to be integrated within a SoC, the accelerator needs to share interfaces with the system. The natural interface exposed by an accelerator engine may be different from that accepted by the broader SoC. In the case of the reference NanoSoC, an AHB-lite bus is utilised. A translation layer needs to be implemented - which has been called a 'wrapper'. The NanoSoC wrapper has external AHB and APB interfaces and will instantiate the accelerator engine and packet constructors, de-constructers and buffers.

The G31 implements the Bifrost architecture supporting OpenGL 2.0 and Vulkan with a simple 1 uni-pixel or dual-pixel shader core operating with a 650 MHz clock, small 4k load/store cache and optimised work registers for low energy and small area.

Bifrost DDKs

Bifrost Android Renderscript

RenderScript is a language and API in Android OS that enables you to use different processors for compute intensive tasks. RenderScript applications can be written to make optimal use of the GPU acceleration capabilities offered by the Mali RenderScript GPU accelerator

System Controllers

Interrupt Controllers

GIC-500 General Interrupt Controller

A Generic Interrupt Controller providing registers for managing interrupt sources, interrupt behavior, and interrupt routing for up to 128 Armv8.0 A class processor cores such as the A53. It implements version 3.0 of the ARM Generic Interrupt Controller Architecture Specification. The GIC-500 has a 64-bit AMBA AXI4 master port to access main memory.

GIC-400 General Interrupt Controller

A Generic Interrupt Controller providing registers for managing interrupts for up to eight Armv7 A class processor cores such as the A7. An AMBA AXI4 slave interface handles message-based interrupts. It supports the generation of all cores (SPI) and core specific (PPI) interrupts through physical signals. It generates signals to the wakeup controller and to the processors to indicate that there are valid pending interrupts.

PL192 Vectored Interrupt Controller

The PL192 VIC moves interrupt control to the AMBA AHB bus to manage service interrupt requests throughout a SoC. Interupts are prioritised, a single Fast Interrupt Request (FIQ) source can be used for special low-latency demands, then 32 vectored IRQ interrupts can be dynamically assigned priority order or will default to 0 through 31 order, finally the PL192 VIC supports daisy chaining with lowest priority. The PL192 VIC provides dedicated hardware control to determine the priority source of interupt and the location of the service routine to handle the request.

TZC-400 TrustZone Address Space Controller

The TZC-400 TrustZone Address Space Controller (TZC-400) implements filters between ACE-Lite masters and ACE-Lite slaves to perform security checks on transactions to memory or peripherals using up to eight separate regions in the address space, each with an individual security level setting. Each filter unit operates in its own clock domain and has an AXI low-power interface for clock gating. Each domain can operate asynchronously from all other domains. It is used in a TrustZone system to implement the security requirements for the SoC.

L2C-310 Level 2 Cache Controller

The Level 2 Cache Controller L2C-310 improves memory access speed within a SoC by implementing Level 2 memory caching (access within 8 cycles) using slave and master AMBA AXI interfaces, between Level 1 instruction and data caches (1-2 cycles) and Level 3 main memory (30-100 cycles). The cache available can be configured from 16KB to 8MB. It supports the TrustZone architecture for enhanced security.

MMU-500 System Memory Management Unit

The MMU-500 System Memory Management Unit provides address and memory attribute translation from Virtual Memory spaces to the Physical Memory within the System on Chip. An SMMU is placed between a device and the system interconnect to translate addresses for Direct Memory Access requests for the device before the requests are passed into the system interconnect. An SMMU might translate traffic from just one device or a set of devices, each device identified by a StreamID. The MMU-500 uses input from the requesting master to identify a context, the resources to use, including th

BP140 AXI Memory Interface

The BP140 AXI Memory Interface provides a single-port memory interface configurable for synchronous SRAM or ROM. It supports all AMBA AXI channels except the low power channel as it does not have a low-power mode of operation. It can be configured with data width of 64 bits or 32 bits. It uses round-robin arbitration between read and write transactions.

BP141 TrustZone Mem. Adapter

The BP141 TrustZone Memory Adapter (TZMA) is an AMBA compliant System-on-Chip peripheral that enables a single physical memory cell of up to 2MB to be shared between a secure and a non-secure partition. It is compatible with the AXI internal memory interface (BP140). The TrustZone Protection Controller (TZPC) sets up memory areas as secure or non-secure. Transactions presented at the AXI slave interface are checked against the current security configuration. If a transaction passes this security check then it is routed through to the AXI master interface.

PCK-600 Power Control Kit

A SoC requires multiple clock and power domains to be efficient. PCK-600 provides components to allow power control infrastructure to be distributed in a SoC in accordance with the Arm Power Control System Architecture using Q-Channel and P-Channel low power interfaces. Clock Controllers (CLK-CTRL) provides High-level Clock Gating (HCG) for a single clock domain.

System-on-Chip (SoC) security depends on architectural and secure IP blocks in order to protect systems, networks, and data from a range of attacks and limit potential vulnerabilities.

Physically Unclonable Function

The use of a Physically Unclonable Function (PUF) for key generation or encryption operations relies on process variation that are intrinsic in the manufacture of devices. In this example a Ring oscillator based PUF is implement. Two banks of ring oscillators are carefully defined to ensure they are as similar as possible so their exact oscillation frequency is only altered by the intrinsic fabrication process variation in their position on the die and not by any other design consideration.

True Random Number Generator

The Arm True Random Number Generator is a component that generates standards compliant random bit streams. It is designed for simple SoC integration connecting via an AMBA APB2 slave interface to the SoC system bus. It is used for actions such as key generation or seeding approved deterministic random number generators. The only clock is rng_clk and no clock gating mechanism implemented.

Corstone Subsystems

Corstone Subsystems combines the various system IP components for a specific processor and Arm architecture to simplify System on Chip designs. The contain reference designs that utilise the IP blocks to reduce design and verification effort.

Corstone 101 for m3

Corstone-101 combines various system IP components for Cortex M3 based System on Chip designs and a subsystem (SSE-050) integrating the processor, memory, debug, security, and power control. It also contains the Cortex-M System Design Kit for SoC designs using the M0, M0+, M3 and m4 processors. It has a selection of AMBA AHB and APB infrastructure components and embedded Flash controllers. The GFC-100 Generic Flash Controller provides the generic system side function that allows a SoC to access eFlash memory.

Corstone 201 for m33

Corstone-201 combines various system IP components for Cortex M based System on Chip designs and a subsystem integrating the processor, memory, debug, security, and power control. It includes example subsystems for Cortex M33 (SSE-200), M23 (SSE-123), M3 (SSE-050) and the Cortex-M System Design Kit.

Corstone 102 for M23

Corstone-102 combines various system IP components for Cortex M23 based System on Chip designs. The M23 core contains TrustZone and Corstone-102 components support Secure and a Non-secure operation as well as interconnect, peripheral, and components that comply with the Armv8-M processor architecture.

Corstone 300 for M55

Corstone-300 combines various system IP components for Cortex M55 based System on Chip designs and the Ethos U55 accelerator for Artificial Intelligence and Machine Learning workloads. Corstone-300 components support TrustZone with system-level Secure and a Non-secure operation. The bus protocols supported are Advanced Extensible Interface (AXI5), Advanced High Performance Bus (AHB5) protocol and Advanced Peripheral Bus (APB4). The PCK-600 Power Control Kit provides components for SoC clock and power control using the Arm Q-Channel and P-Channel low power interfaces. The GFC-200

Corstone 500 for A5

Corstone-500 combines various system IP components for Cortex A5 Linux capable System on Chip designs using the AMBA protocol NIC-400 for up to 128 masters and 64 slaves, SoC-400 components for debug and trace and other Arm IP. On-chip secondary cache can be added with the L2C-310 Level 2 Cache Controller. For early software prototyping there is a Fixed Virtual Platform (FVP) Fast Model simulator and a ready prepared FPGA image.

Peripherals

Arm System IP provides support for a variety of peripheral controllers which are usually managed in a sub-system based around the Advanced Microcontroller Bus Architecture (AMBA) Advanced Peripheral Bus (APB) which has reduced complexity interfaces, lower frequency operation and data width (32 bits) compared to the Advanced High-performance Bus (AHB). Using a secondary APB bus appearing as a single AHB or ASB slave on the main system bus reduces power consumption and improves overall SoC efficiency.

PL011 UART is an Advanced Microcontroller Bus Architecture (AMBA) slave module that connects to the Advanced Peripheral Bus (APB) used for serial communications. It supports Direct Memory Access (DMA) operations, 32×8 transmit and 32×12 receive First-In, First-Out (FIFO) memory buffers and an Infrared Data Association (IrDA) Serial InfraRed (SIR) protocol ENcoder/DECoder block.

PL022 SPI - Synchronous Serial Port

PL022 SPI Synchronous Serial Port is an Advanced Microcontroller Bus Architecture (AMBA) slave module that connects to the Advanced Peripheral Bus (APB) used for synchronous serial communication with slave or master peripherals. It supports Direct Memory Access (DMA) operations, 16 bits wide, 8 locations deep transmit and receive first-in, first-out (FIFO) memory buffers, and a choice of interface, Motorola SPI, National Semiconductor Microwire, or Texas Instrument synchronous serial.

PL031 RTC Real Time Clock

PL031 RTC is an Advanced Microcontroller Bus Architecture (AMBA) slave module that connects to the Advanced Peripheral Bus (APB) used provide a basic alarm function or long time base counter. A 32-bit free-running counter is incremented on successive rising edges of the 1Hz clock signal input. The counter and match values are compared in a comparator which triggers a maskable interrupt that can be used to implement a basic time alarm function.

CoreLink DMA-230

DMA-230 is a low gate count (3-10k gates) DMA controller that is compatible with the Advanced Microcontroller Bus Architecture (AMBA) AHB-Lite protocol using a single AHB-Lite master for transferring data using 32-bit address and data buses. It perform memory-to-memory, memory-to-peripheral and peripheral-to-memory transfers and allows slow peripherals to stall the completion of a DMA cycle.

CoreLink DMA-330

The DMAC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral that is developed, tested, and licensed by ARM. The DMAC provides an AXI master interface to perform the DMA transfers and two APB slave interfaces that control its operation. The DMAC implements TrustZone secure technology with one APB interface operating in the Secure state and the other operating in the Non-secure state.

Corelink DMA-350

The DMA 350 is a high performance, high gate count DMA controller. It uses one or two AMBA AXI5 master interfaces to perform DMA transfers, with an APB4 interface to set and read control registers. The DMA350 can also be configured with stream interfaces used to perform operations on the data as it moves through the DMA. The DMA can be configured with a bootrom to set control registers at boot. And can be enabled in software, with interrupts or over the trigger interfaces. DMA transfer types include 1D, 2D, wrap and template.

Debug & Trace

No matter how much work is done to ensure a design is correct it is likely issues will need to be discovered, identified and corrected. Ensuring an effective and efficient debug environment is important. As a design evolves towards a physical implementation the debug and trace environment needs the be established and maintained.

SoC-600 supports the Arm Debug Interface (ADI) v6 Architecture to build debug and trace into a SoC design. It can route debug and trace data over system master interfaces removing the need for a dedicated debug interface. The debug and trace over functional interface connections such as USB or wireless.

CoreSight SoC-400 is a debug subsystem design with Arm IP blocks for debug and trace in support of multi-processor SoCs. It contains components to implement CoreSight functionality for debug, trace, cross-triggering and timestamps. The debug subsystem components for access and control of the system, sources that generate trace data, links that flow of trace data through the system, sinks that collect trace data and timestamps for the system. access and control is via the Debug Access Port and the Embedded Cross Trigger supporting

The Arm CoreSight Secure Debug Channel provides protection against debug access attacks allowing a debug certificate to be exchanged through a dedicated communication path for authenticating debug accesses. The block is used with other Arm Security IP to establish a secure communication protocol to ensure only authenticated access to the SoC via the debug system.

The Arm CoreSight System Trace Macrocell (STM) - 500 is a trace source that provides trace data which conforms to the MIPI System Trace Protocol version 2 and provides timing-accurate trace data that is especially suitable for real-time applications. The STM-500 can receive instrumentation data from multiple processors and processes via the AXI slave interface or generate trace when signals are asserted on the hardware event interface. The Arbiter selects the input data with higher priority assigned to AXI transactions p

System Trace Macrocell

The Arm CoreSight System Trace Macrocell (STM) is a trace source that supports multiple processor cores and other components such as Direct Memory Access (DMA) controllers to pass trace data into the debug system. It is a successor to the Instrumentation Trace Macrocell (ITM) using an AXI slave interface to provide higher throughput of trace data from SoC components.

Trace Memory Controller

The Trace Memory Controller (TMC) enables trace data to be passed to system memory and other high speed devices and links in the System-on-Chip as part of the debug system. Debug system designs include the following components: Embedded Trace Buffer (ETB) enables trace data to be stored in a dedicated SRAM, used as a Circular Buffer. Embedded Trace FIFO (ETF) enabled trace data to be stored used either as a Circular Buffer or as a FIFO. Embedded Trace Router (ETR) enables trace data to be routed over an AXI bus to system memory or other AXI slaves.

Tools & Models

Tools and Models to support the SoC design and fabrication process provided by Arm as part of the AAA programme and by the SoC Labs community.

COIL-3D: A CAD Tool for the Optimisation of Inductive Links in 3D-ICs

COIL-3D is a CAD tool for determining best performing inductor geometries for use in Inductive Coupling Link (ICL) based Three Dimensional Integrated Circuits (3D-ICs), developed at the University of Southampton, in collaboration with Arm Research. The tool takes as its inputs a configuration file (*.cfg) describing the physical and electrical parameters required for the design and then generates an inductor layout to maximise the performance of the inductive channel, for data transmission at a given frequency. COIL-3D consists of two main elements: The solver: a set of mathematical expre

Socrates Interconnect tool

Socrates assists in the design of a SoC interconnect by configuring the various Arm IP components (from the Arm IP catalog) to help the designer create an optimized and viable CoreLink Interconnect. It includes design rule checks to help validate complex on-chip AMBA® interconnects to ensure Quality of Service (QoS), timing closure, low latency, Coherency, Virtualization and manage multiple power and voltage domains. It allows designers to maintain a high-level specification in a configuration that can be shared and re-used reduce the design effort for a new SoC.

Arm DS-Gold

Arm Development Studio is a professional software development solution for bare-metal embedded systems and Linux-based systems.

Virtual system models

Arm Fast Models provide a programming view simulation of Arm IP with profiling, debug and trace that allow software and hardware to be designed without the need for hardware, they support not just processors (Instruction Set Simulation) but memory and peripherals for complete system simulation. Fast Models can be integrated into the wider SoC design process with interface to EDA tools and other IP block simulation steps.

Microcontroller Development Kit (MDK) for Armv8-M Architecture provides an integrated development environment (IDE) for developing embedded applications aimed at Arm Cortex-M processors including C/C++ compilers, various middleware components, as well as support for various debug adapters to connect to development boards. Cortex Microcontroller Software Interface Standard (CMSIS) is a software framework for embedded Cortex-M applications including Real Time Operating Sytem (CMSIS-RTOS), over 60 functions for digital signal processing (CMSIS-DSP) and API support for peripheral drive

A full-system SystemC-based simulator for intermittent computing and energy-driven SoCs accurately modelling the interplay between energy-availability, power consumption, and execution in a closed feedback loop. The power model is based on recording high-level events (memory accesses, peripheral operations etc.) and states (modules on/off, peripheral operation modes etc.), and computing the instantaneous power consumption at runtime. Simultaneously, external circuitry such as, energy storage, power supply and power management are modelled.