Below you will find information on community projects, the specific project pages have links to the 'technology' and 'design flow' stages used and ways you can comment on or join a project.

Projects are key to community hardware design

As a community hardware design activity we form our collaborations around shared design actions making Projects a core of the SoC Labs community. Projects help us share and reuse hardware and software developments around core Arm IP to help us in our research goals.

A project, takes technology and uses a design flow to make a SoC.

A project has a timeframe and uses the two other significant aspects of a SoC development, the selection of technology or IP blocks that make up the SoC and the design flow that is followed from specification through to final instantiation of a system. Any System On Chip usually involves the use of pre-existing IP blocks. A project team can select IP from the technology section of the site during the first stage of a design flow, Architectural Design. Later stages in the design flow support the creation of the novel aspects of the SoC design.

Projects have a type, either active, complete (case study) or being formulated (request for collaboration)

Sharing information on projects much earlier than traditional academic collaboration is encouraged. Historically knowledge sharing has been at the end of the research activity, with published papers and results. As well as write up of finished projects ("case study"), ongoing projects under development ("projects") there are projects that are still being formulated ("request for collaboration") listed. We want to encourage people to engage with the project teams, for example, adding a comment to a specific project page or joining a project.

Latest Collaborative Projects

Latest Competition Projects

Latest Completed Project Milestones

Project Name Target Date Completed Date Description
Project Milestone Overview example Tape Out

Test add

Project Milestone Overview example Standard Cell Libraries
Project Milestone Overview example Clock Tree Synthesis
Project Milestone Overview example Generate RTL
Project Milestone Overview example Synthesis
Project Milestone Overview example Simulation
Project Milestone Overview example Architectural Design
Project Milestone Overview example Technology Selection
Project Milestone Overview example Specifying a SoC

Test

BlackBear : A reconfigurable AI inference accelerator for large image applications Milestone #6
  • Verifying communication types without data exchange in Data Link Layer Protocol
    • PE-Tile: Implement the Network Interface Controller (NIC), the Direct Memory Access (DMA), and a debug module acting as a PCU to finish communication procedures.
    • Control subsystem: Implement a baremetal runtime running on the processor in the Processing System of our FPGA board.
    • Verify hardware correctness with RTL simulation.
    • Prototype the hardware design on our FPGA board and co-simulate with the runtime to monitor the process of each target communication types.
  • Verifying communication types with data exchange in Data Link Layer Protocol
    • PE-Tile
      • Enhance the Network Interface Controller (PE-NIC), the Direct Memory Access (DMA), and the debug module acting as a PCU.
      • Implement the Shared Memory Controller (SMC) to handle memory access requests from PE-Tile system bus and data copy operations through NoC interconnects.
    • Control subsystem: Implement a baremetal runtime running on the processor in the Processing System of our FPGA board.
    • Global cache memory: Implement the Cache Network Interface Controller (Cache-NIC) and cache controller to accept requests from components attached on NoCs and return corresponding response.
    • The RTL verification and FPGA prototyping will be finished in the next milestone.

Latest Project Updates