Clock Tree Synthesis

Clock Tree Synthesis starts the process of signal routing considering the most time critical signals. The aim is to distribute the clock signal to all the design elements to avoid skew and minimise latency.

The work involves both clock tree building and clock tree balancing. There are various structures for clock trees, H and X shapes, fishbone, spines, etc. and can have multiple decompositions. Clock tree inverters are placed equidistant to keep the pulse widths symmetrical to ensure edge triggered events. Balancing a tree involves adding clock tree buffers (CTB) for clock skew reduction. Careful use of clock tree inverters and buffers minimises area and power demands.

The outputs are Design Exchange Format (DEF), Standard Parasitic Exchange Format (SPEF), and Netlist files.