Projects - Collaborative

View Collaborative Projects

Daniel Newbrook

The integration of the DMA350 into the nanosoc re-usable SoC architecture will improve the transfer bandwidth on DMA channels within the SoC. This project integrates the DMA 350 into nanosoc, validates the integration and functionality of the DMA 350, and compares the performance of the DMA 350 to the PL230, that was the initial DMA controller integrated into nanosoc.

Collaborative

Active Project

Corelink DMA-350

CoreLink DMA-230

System Verification of NanoSoC

David Mapstone

Performing system-level verification on a System-on-Chip (SoC) design is crucial for ensuring the correct function and overall performance of the entire system, rather than individual components. With NanoSoC, there are multiple options for performing system-level verification.

Collaborative

Active Project

XHB-400: AXI4 to AHB-Lite Bridge

Building system-optimised AMBA interconnect

David Flynn

Example case-study of using the Arm CMSDK AMBA-AHB Bus-Matrix tools to build system-optimised interconnect.

SHA-2 Accelerator Engine

David Mapstone

Motivation

At SoC Labs, we have need of an accelerator to test our SoC infrastructure and confirmation of our accelerator wrapper design to get size and performance information as well as to try and get ahead and uncover potential problems researchers may experience trying to put their IP into the reference SoC.

Specification

The preliminary design has been broken into two main blocks:

Collaborative

Active Project

Lightweight DMA Infrastructure

Daniel Newbrook

The project aims to produce lightweight SoC Infrastructures using the variety of AMBA bus architectures. An initial NanoSoC infrastructure using AHB for small scale accelerators with low data throughput and complexity is complete. The project is now looking for collaboration on an AXI based SOC, for larger scale accelerators with higher data throughput and added complexity.

Collaborative

Request of Collaboration

CoreLink DMA-230

Hardware design

Getting Started with SoC Labs

Architectural Design

Efficient Keyword-Spotting on an Arm M7 microcontroller

Epifanios Baikas

This 4 month PhD Interdisciplinary Team Project used an Arm M7 to measure actual energy used in different forms of inference and feature extraction for keyword spotting.

Arm Cortex-M0 microcontroller

David Flynn

A reference design based on an Arm Cortex-M0 CPU and the Cortex-M0 Design Kit provided in the Corstone-101 subsystem package, available under the Arm Academic Access agreement.

Fused: Closed-loop Performance and Energy Simulation of Embedded Systems

Samuel

Fused is a full-system simulator for modelling energy-driven computers. To accurately model the interplay between energy-availability, power consumption, and execution; Fused models energy and execution in a closed feedback loop.

Hardware SoC bus level debug agent (v4)

David Flynn

A hardware Finite State Machine on-chip AMBA interconnect controller using a serial ASCII debug protocol, with functional upgrades to Version 4 to support 8-, 16- and 32-bit accesses, to facilitate off-chip validation.

3D-stacked cortex-M0 SoC with wireless inter-tier data and power transfer

John Darlington

This project developed a 2-tier 3D-stacked Cortex-M0 SoC, in 65nm CMOS technology, with wireless inter-tier power and data transfer through an inductively coupled bus which achieved 20.3Gbps/mm2 data, and 7.1mW/mm2 power transfer simultaneously through a 250 µm channel. At the time of publishing it was the smallest ever reported inductive data and power link.

Collaborative

Case Study

Cortex-M0