John Darlington

Interests

Once a System on Chip (SoC) design has fabricated in a foundry the individual items need to be put into an electronic package that protects it from the external environment and also interconnects it to other parts of a larger system, often a Printed Circuit Board. The package may also need to perform other functions such as transfer of heat or protection from emissions that could affect device performance.

Is not a programming language, it is an IEEE Standard C++ class library for system and hardware design. Knowledge of the SystemC library allows it to be extended using the C++ language to enable SoC design and verification activities. A SystemC application usually has an elaboration phase during which a module hierarchy is instantiated that represents the hardware design for the system, followed by a simulation phase using a simulation engine which is formed as part of the core of the SystemC library which schedules the user defined processes that simulate the design. Arm provides a num

SoC Labs site

This area of interest is for this web site, the SoC Labs community portal. Here we discuss the site's structure, operations and any issues the community feel need improvement. If you are new to SoC Labs, then knowing how we structure information on the site will help. Projects: As a community activity we form our collaborations around shared Projects.

All content on the SoC Labs portal is moderated. This is to ensure the content is useful to the community. Once signed up, you can make suggested changed to material on the portal, create new material, etc.

Site structure

Projects Community centric hardware design projects are the core activity of the SoC Labs. We are keen to share information on projects much earlier than traditional academic sharing. Historically knowledge sharing has been at the end of the research activity, with published papers and results. We are keen to get collaborations started much earlier. So as well as write up of finished projects ("case studies"), ongoing projects under development ("projects") and even projects that are still being formulated ("request for collaboration") are listed.

Corstone 102 for M23

Corstone-102 combines various system IP components for Cortex M23 based System on Chip designs. The M23 core contains TrustZone and Corstone-102 components support Secure and a Non-secure operation as well as interconnect, peripheral, and components that comply with the Armv8-M processor architecture.

Corstone 300 for M55

Corstone-300 combines various system IP components for Cortex M55 based System on Chip designs and the Ethos U55 accelerator for Artificial Intelligence and Machine Learning workloads. Corstone-300 components support TrustZone with system-level Secure and a Non-secure operation. The bus protocols supported are Advanced Extensible Interface (AXI5), Advanced High Performance Bus (AHB5) protocol and Advanced Peripheral Bus (APB4). The PCK-600 Power Control Kit provides components for SoC clock and power control using the Arm Q-Channel and P-Channel low power interfaces. The GFC-200

Corstone 500 for A5

Corstone-500 combines various system IP components for Cortex A5 Linux capable System on Chip designs using the AMBA protocol NIC-400 for up to 128 masters and 64 slaves, SoC-400 components for debug and trace and other Arm IP. On-chip secondary cache can be added with the L2C-310 Level 2 Cache Controller. For early software prototyping there is a Fixed Virtual Platform (FVP) Fast Model simulator and a ready prepared FPGA image.

Ethos-U55 is a micro Neural Processing Unit coprocessor to accelerate machine learning inference with a configurable 32 to 256 multiply-accumulate (MAC) engine. One of the features to minimise memory use is that weights are losslessly compressed as part of a compiled command stream with the unit undertaking weight decompression. The unit executes the command stream with local DMA access to system memory.

SoC-600 supports the Arm Debug Interface (ADI) v6 Architecture to build debug and trace into a SoC design. It can route debug and trace data over system master interfaces removing the need for a dedicated debug interface. The debug and trace over functional interface connections such as USB or wireless.

Interrupt Controllers

PCK-600 Power Control Kit

A SoC requires multiple clock and power domains to be efficient. PCK-600 provides components to allow power control infrastructure to be distributed in a SoC in accordance with the Arm Power Control System Architecture using Q-Channel and P-Channel low power interfaces. Clock Controllers (CLK-CTRL) provides High-level Clock Gating (HCG) for a single clock domain.

Universal Verification Methodology

The Universal Verification Methodology (UVM) is a standard to create a modular reusable generic verification environment. It aims to reduce the effort of reusing IP by making it easier to reuse verification components associated with the IP. UVM provides an architectural framework and class libraries for establishing verification environments for a Design Under Test (DUT). A Testbench is a flexible way to create a structured approach to verify IP.

Standard Cell Libraries

Standard Cell libraries help simplify the design task by abstracting some of the complexity of physical transistor layout and local connection while still understanding the design tradeoffs to meet the system level goals for power, area, and performance for a system-on-chip (SoC). Standard Cell libraries are a collection of well characterised basic circuits that Electronic Design Automation (EDA) tools use to instantiate the larger design based on the design constraints (optimisation choices, timing, etc.).

Memory generators

In any SoC design memory makes up a significant portion of the transistor count and area. Small memories can be synthesized using flip-flop or latch standard cells, but synthesizing large memories is inefficient in area, energy, and timing compared to using custom bits in a memory block.

SoC Design Contest 2023 example flow

SoC Labs and Arm have announced a joint 'Bridging the Skills Gap' SoC Design Contest that will run during 2023. This example design flow is provided to help groups engage with the contest. It is not prescriptive but tries to provide useful information in creating a design flow environment in which to develop your SoC design. The information covers example design flow elements that can be used as a basis for your design flow for taking part in the competition. You are free to use a design flow of your own if you have already established methods.

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Authored Comments

Subject	Comment	Link to Comment
Similar work	Some interesting parallel work is presented here by Michele Magno from ETH Zurich. tinyML Talks - Michele Magno: LW Embedded Gesture Recognition Using Novel Short-Range Radar Sensors - YouTube The same areas of concern, feature extraction, choice and model optimisation, etc. A variation of the input medium but target similar application in terms of human to machine interaction. Some investigation on the Arm M7 microcontroller as well as alternative hardware.	view
Should this really be in Physical Design under Design Flow	The SoC Labs site is still evolving and we may not get things in exactly the right place to start with. A few people have felt this Interest is really a stage in the Physical Design and part of an ASIC design flow. On reflection I agree.	view
Creating a PhD Portfolio in SoC Labs	How about creating an item describing how best to create a PhD Portfolio in SoC Labs?	view
Design Flow information structure	We have an initial view that has the four high level generic stages of the design flow and then an area where we describe specific example flows. Hopefully we will add some more example flows to David’s initial ‘example flow’ for the Xilinx(R) PYNQ(R) platform. As we develop some additional example flows we will try and discuss how the flow delivers the requirement of the general design flow steps.	view
Design Flow information structure	I added a comment in the example design flow to describe the basic structure ot the 'design flows' area of the site. FPGA SoC prototyping with Xilinx(R) PYNQ(R) platform \| SoC Labs The principle is that the area four high level generic stages that descibe the necessary steps in any design flow implementation and then there is an additional area where we describe specific example flows. As we add additional example flows we should aim to discuss within their descriptions how the specific flow implementation delivers the requirement of the general design flow steps.	view
Creating a PhD Portfolio in SoC Labs	I was wondering if people had any initial views on this? Otherwise we can create something in an agile way and people can see if it has utility Happy do this agile or in a more system engineering way by building a 'Requirements Definition'.	view
Notifications	We have been implementing some improvements to notifications. People can choose their preferences for notifications in their profile. Our general view is that people will want to get notification on how others in the community view their contributions. For example the site will notify people when comments are responded to and liked/disliked. We are happy to adjust these things based on community feedback so please do let us know your views,	view
Sign Up Link	Hi, In the mean time, adding a comment worked and I have added you. Whatever works, if people express and interest we will make sure we note it. Looking forward to working with you on this. John.	view
Some slight difference in types of content	One initial feedback from the community on the site is that there is some difference in terms of being an author for an Article and being an author of something in the subject tree areas such as Technology, Interests and Design Flows. Items in subject trees such as Technology, Interests and Design Flows are considered to be shared by the community currently. Once you have created it, you can't delete it yourself. Why? they ask. Let us take the example of a Project, if people have declared an interest in the project then why should the person who started it be allowed to take what has become a community interest away? As long as the community wants to take it forward then that is fine. Articles are currently not considered shared and usually have some timeliness criteria so can be currently be deleted. If an author wants something deleted they can prepare a revision and submit for moderation, they can request moderation to delete the item completely. I hope this helps.	view
A new example flow has been…	A new example flow has been published to support the SoC Design Contest for 2023.	view

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